
clock_tree.o:     file format elf32-littlearm


Disassembly of section .text:

00000000 <main>:
   0:	e92d4800 	push	{fp, lr}
   4:	e28db004 	add	fp, sp, #4
   8:	e24dd008 	sub	sp, sp, #8
   c:	e59f00d8 	ldr	r0, [pc, #216]	; ec <main+0xec>
  10:	e3a0100c 	mov	r1, #12
  14:	e59f20d4 	ldr	r2, [pc, #212]	; f0 <main+0xf0>
  18:	e59f30d4 	ldr	r3, [pc, #212]	; f4 <main+0xf4>
  1c:	ebfffffe 	bl	0 <printf>
  20:	e3a00008 	mov	r0, #8
  24:	ebfffffe 	bl	0 <malloc>
  28:	e1a03000 	mov	r3, r0
  2c:	e50b3008 	str	r3, [fp, #-8]
  30:	e51b3008 	ldr	r3, [fp, #-8]
  34:	e3530000 	cmp	r3, #0
  38:	1a000003 	bne	4c <main+0x4c>
  3c:	e59f00b4 	ldr	r0, [pc, #180]	; f8 <main+0xf8>
  40:	ebfffffe 	bl	0 <puts>
  44:	e3e03000 	mvn	r3, #0
  48:	ea000024 	b	e0 <main+0xe0>
  4c:	e51b3008 	ldr	r3, [fp, #-8]
  50:	e59f20a4 	ldr	r2, [pc, #164]	; fc <main+0xfc>
  54:	e5832000 	str	r2, [r3]
  58:	e51b0008 	ldr	r0, [fp, #-8]
  5c:	e3a01000 	mov	r1, #0
  60:	ebfffffe 	bl	0 <tree_alloc>
  64:	e1a02000 	mov	r2, r0
  68:	e59f3090 	ldr	r3, [pc, #144]	; 100 <main+0x100>
  6c:	e5832000 	str	r2, [r3]
  70:	e59f3088 	ldr	r3, [pc, #136]	; 100 <main+0x100>
  74:	e5933000 	ldr	r3, [r3]
  78:	e3530000 	cmp	r3, #0
  7c:	1a000001 	bne	88 <main+0x88>
  80:	e3e03000 	mvn	r3, #0
  84:	ea000015 	b	e0 <main+0xe0>
  88:	e59f3070 	ldr	r3, [pc, #112]	; 100 <main+0x100>
  8c:	e5933000 	ldr	r3, [r3]
  90:	e1a00003 	mov	r0, r3
  94:	ebfffffe 	bl	108 <clock_dir_scan>
  98:	e1a03000 	mov	r3, r0
  9c:	e3530000 	cmp	r3, #0
  a0:	0a00000c 	beq	d8 <main+0xd8>
  a4:	e51b3008 	ldr	r3, [fp, #-8]
  a8:	e5933000 	ldr	r3, [r3]
  ac:	e59f0050 	ldr	r0, [pc, #80]	; 104 <main+0x104>
  b0:	e1a01003 	mov	r1, r3
  b4:	ebfffffe 	bl	0 <printf>
  b8:	e51b0008 	ldr	r0, [fp, #-8]
  bc:	ebfffffe 	bl	0 <free>
  c0:	e59f3038 	ldr	r3, [pc, #56]	; 100 <main+0x100>
  c4:	e5933000 	ldr	r3, [r3]
  c8:	e1a00003 	mov	r0, r3
  cc:	ebfffffe 	bl	0 <tree_free>
  d0:	e3e03000 	mvn	r3, #0
  d4:	ea000001 	b	e0 <main+0xe0>
  d8:	ebfffffe 	bl	510 <fill_clock_tree>
  dc:	e3a03000 	mov	r3, #0
  e0:	e1a00003 	mov	r0, r3
  e4:	e24bd004 	sub	sp, fp, #4
  e8:	e8bd8800 	pop	{fp, pc}
  ec:	00000000 	andeq	r0, r0, r0
  f0:	00000008 	andeq	r0, r0, r8
  f4:	0000000c 	andeq	r0, r0, ip
  f8:	00000010 	andeq	r0, r0, r0, lsl r0
  fc:	0000003c 	andeq	r0, r0, ip, lsr r0
 100:	00000000 	andeq	r0, r0, r0
 104:	00000060 	andeq	r0, r0, r0, rrx

00000108 <clock_dir_scan>:
 108:	e92d4800 	push	{fp, lr}
 10c:	e28db004 	add	fp, sp, #4
 110:	e24ddf62 	sub	sp, sp, #392	; 0x188
 114:	e50b0188 	str	r0, [fp, #-392]	; 0x188
 118:	e51b3188 	ldr	r3, [fp, #-392]	; 0x188
 11c:	e593301c 	ldr	r3, [r3, #28]
 120:	e5933000 	ldr	r3, [r3]
 124:	e59f0258 	ldr	r0, [pc, #600]	; 384 <clock_dir_scan+0x27c>
 128:	e1a01003 	mov	r1, r3
 12c:	ebfffffe 	bl	0 <printf>
 130:	e51b3188 	ldr	r3, [fp, #-392]	; 0x188
 134:	e593301c 	ldr	r3, [r3, #28]
 138:	e5933000 	ldr	r3, [r3]
 13c:	e1a00003 	mov	r0, r3
 140:	ebfffffe 	bl	0 <opendir>
 144:	e50b000c 	str	r0, [fp, #-12]
 148:	e51b300c 	ldr	r3, [fp, #-12]
 14c:	e3530000 	cmp	r3, #0
 150:	1a000075 	bne	32c <clock_dir_scan+0x224>
 154:	e51b3188 	ldr	r3, [fp, #-392]	; 0x188
 158:	e593301c 	ldr	r3, [r3, #28]
 15c:	e5933000 	ldr	r3, [r3]
 160:	e59f0220 	ldr	r0, [pc, #544]	; 388 <clock_dir_scan+0x280>
 164:	e1a01003 	mov	r1, r3
 168:	ebfffffe 	bl	0 <printf>
 16c:	e3e03000 	mvn	r3, #0
 170:	ea000080 	b	378 <clock_dir_scan+0x270>
 174:	e51b3184 	ldr	r3, [fp, #-388]	; 0x184
 178:	e3530000 	cmp	r3, #0
 17c:	0a000077 	beq	360 <clock_dir_scan+0x258>
 180:	e51b3184 	ldr	r3, [fp, #-388]	; 0x184
 184:	e5d3300b 	ldrb	r3, [r3, #11]
 188:	e353002e 	cmp	r3, #46	; 0x2e
 18c:	0a000068 	beq	334 <clock_dir_scan+0x22c>
 190:	e51b3188 	ldr	r3, [fp, #-392]	; 0x188
 194:	e593301c 	ldr	r3, [r3, #28]
 198:	e5933000 	ldr	r3, [r3]
 19c:	e24b2018 	sub	r2, fp, #24
 1a0:	e1a00002 	mov	r0, r2
 1a4:	e59f11e0 	ldr	r1, [pc, #480]	; 38c <clock_dir_scan+0x284>
 1a8:	e1a02003 	mov	r2, r3
 1ac:	ebfffffe 	bl	0 <asprintf>
 1b0:	e50b0008 	str	r0, [fp, #-8]
 1b4:	e51b3008 	ldr	r3, [fp, #-8]
 1b8:	e3530000 	cmp	r3, #0
 1bc:	aa000001 	bge	1c8 <clock_dir_scan+0xc0>
 1c0:	e3e03000 	mvn	r3, #0
 1c4:	ea00006b 	b	378 <clock_dir_scan+0x270>
 1c8:	e51b3018 	ldr	r3, [fp, #-24]
 1cc:	e1a00003 	mov	r0, r3
 1d0:	ebfffffe 	bl	0 <basename>
 1d4:	e1a03000 	mov	r3, r0
 1d8:	e3530000 	cmp	r3, #0
 1dc:	0a000001 	beq	1e8 <clock_dir_scan+0xe0>
 1e0:	e3a03000 	mov	r3, #0
 1e4:	ea000000 	b	1ec <clock_dir_scan+0xe4>
 1e8:	e3e03000 	mvn	r3, #0
 1ec:	e50b3008 	str	r3, [fp, #-8]
 1f0:	e51b3008 	ldr	r3, [fp, #-8]
 1f4:	e3530000 	cmp	r3, #0
 1f8:	ba000041 	blt	304 <clock_dir_scan+0x1fc>
 1fc:	e51b2018 	ldr	r2, [fp, #-24]
 200:	e51b3184 	ldr	r3, [fp, #-388]	; 0x184
 204:	e283300b 	add	r3, r3, #11
 208:	e24b101c 	sub	r1, fp, #28
 20c:	e1a00001 	mov	r0, r1
 210:	e59f1178 	ldr	r1, [pc, #376]	; 390 <clock_dir_scan+0x288>
 214:	ebfffffe 	bl	0 <asprintf>
 218:	e50b0008 	str	r0, [fp, #-8]
 21c:	e51b3008 	ldr	r3, [fp, #-8]
 220:	e3530000 	cmp	r3, #0
 224:	ba000038 	blt	30c <clock_dir_scan+0x204>
 228:	e51b201c 	ldr	r2, [fp, #-28]
 22c:	e24b3074 	sub	r3, fp, #116	; 0x74
 230:	e1a00002 	mov	r0, r2
 234:	e1a01003 	mov	r1, r3
 238:	ebfffffe 	bl	0 <stat>
 23c:	e50b0008 	str	r0, [fp, #-8]
 240:	e51b3008 	ldr	r3, [fp, #-8]
 244:	e3530000 	cmp	r3, #0
 248:	1a000026 	bne	2e8 <clock_dir_scan+0x1e0>
 24c:	e51b3064 	ldr	r3, [fp, #-100]	; 0x64
 250:	e2033a0f 	and	r3, r3, #61440	; 0xf000
 254:	e3530901 	cmp	r3, #16384	; 0x4000
 258:	1a000025 	bne	2f4 <clock_dir_scan+0x1ec>
 25c:	e3e03000 	mvn	r3, #0
 260:	e50b3008 	str	r3, [fp, #-8]
 264:	e3a00008 	mov	r0, #8
 268:	ebfffffe 	bl	0 <malloc>
 26c:	e1a03000 	mov	r3, r0
 270:	e50b3010 	str	r3, [fp, #-16]
 274:	e51b301c 	ldr	r3, [fp, #-28]
 278:	e1a00003 	mov	r0, r3
 27c:	ebfffffe 	bl	0 <strdup>
 280:	e1a03000 	mov	r3, r0
 284:	e1a02003 	mov	r2, r3
 288:	e51b3010 	ldr	r3, [fp, #-16]
 28c:	e5832000 	str	r2, [r3]
 290:	e51b3188 	ldr	r3, [fp, #-392]	; 0x188
 294:	e5933018 	ldr	r3, [r3, #24]
 298:	e2833001 	add	r3, r3, #1
 29c:	e51b0010 	ldr	r0, [fp, #-16]
 2a0:	e1a01003 	mov	r1, r3
 2a4:	ebfffffe 	bl	0 <tree_alloc>
 2a8:	e50b0014 	str	r0, [fp, #-20]
 2ac:	e51b3014 	ldr	r3, [fp, #-20]
 2b0:	e3530000 	cmp	r3, #0
 2b4:	0a00000d 	beq	2f0 <clock_dir_scan+0x1e8>
 2b8:	e51b0188 	ldr	r0, [fp, #-392]	; 0x188
 2bc:	e51b1014 	ldr	r1, [fp, #-20]
 2c0:	ebfffffe 	bl	0 <tree_add_child>
 2c4:	e51b3188 	ldr	r3, [fp, #-392]	; 0x188
 2c8:	e5933014 	ldr	r3, [r3, #20]
 2cc:	e2832001 	add	r2, r3, #1
 2d0:	e51b3188 	ldr	r3, [fp, #-392]	; 0x188
 2d4:	e5832014 	str	r2, [r3, #20]
 2d8:	e51b0014 	ldr	r0, [fp, #-20]
 2dc:	ebfffffe 	bl	108 <clock_dir_scan>
 2e0:	e50b0008 	str	r0, [fp, #-8]
 2e4:	ea000002 	b	2f4 <clock_dir_scan+0x1ec>
 2e8:	e1a00000 	nop			; (mov r0, r0)
 2ec:	ea000000 	b	2f4 <clock_dir_scan+0x1ec>
 2f0:	e1a00000 	nop			; (mov r0, r0)
 2f4:	e51b301c 	ldr	r3, [fp, #-28]
 2f8:	e1a00003 	mov	r0, r3
 2fc:	ebfffffe 	bl	0 <free>
 300:	ea000002 	b	310 <clock_dir_scan+0x208>
 304:	e1a00000 	nop			; (mov r0, r0)
 308:	ea000000 	b	310 <clock_dir_scan+0x208>
 30c:	e1a00000 	nop			; (mov r0, r0)
 310:	e51b3018 	ldr	r3, [fp, #-24]
 314:	e1a00003 	mov	r0, r3
 318:	ebfffffe 	bl	0 <free>
 31c:	e51b3008 	ldr	r3, [fp, #-8]
 320:	e3530000 	cmp	r3, #0
 324:	1a00000f 	bne	368 <clock_dir_scan+0x260>
 328:	ea000002 	b	338 <clock_dir_scan+0x230>
 32c:	e1a00000 	nop			; (mov r0, r0)
 330:	ea000000 	b	338 <clock_dir_scan+0x230>
 334:	e1a00000 	nop			; (mov r0, r0)
 338:	e24b2d06 	sub	r2, fp, #384	; 0x180
 33c:	e24b3f61 	sub	r3, fp, #388	; 0x184
 340:	e51b000c 	ldr	r0, [fp, #-12]
 344:	e1a01002 	mov	r1, r2
 348:	e1a02003 	mov	r2, r3
 34c:	ebfffffe 	bl	0 <readdir_r>
 350:	e1a03000 	mov	r3, r0
 354:	e3530000 	cmp	r3, #0
 358:	0affff85 	beq	174 <clock_dir_scan+0x6c>
 35c:	ea000002 	b	36c <clock_dir_scan+0x264>
 360:	e1a00000 	nop			; (mov r0, r0)
 364:	ea000000 	b	36c <clock_dir_scan+0x264>
 368:	e1a00000 	nop			; (mov r0, r0)
 36c:	e51b000c 	ldr	r0, [fp, #-12]
 370:	ebfffffe 	bl	0 <closedir>
 374:	e3a03000 	mov	r3, #0
 378:	e1a00003 	mov	r0, r3
 37c:	e24bd004 	sub	sp, fp, #4
 380:	e8bd8800 	pop	{fp, pc}
 384:	00000080 	andeq	r0, r0, r0, lsl #1
 388:	000000ac 	andeq	r0, r0, ip, lsr #1
 38c:	000000dc 	ldrdeq	r0, [r0], -ip
 390:	000000e0 	andeq	r0, r0, r0, ror #1

00000394 <clock_alloc>:
 394:	e92d4800 	push	{fp, lr}
 398:	e28db004 	add	fp, sp, #4
 39c:	e24dd008 	sub	sp, sp, #8
 3a0:	e3a0001c 	mov	r0, #28
 3a4:	ebfffffe 	bl	0 <malloc>
 3a8:	e1a03000 	mov	r3, r0
 3ac:	e50b3008 	str	r3, [fp, #-8]
 3b0:	e51b3008 	ldr	r3, [fp, #-8]
 3b4:	e3530000 	cmp	r3, #0
 3b8:	0a000003 	beq	3cc <clock_alloc+0x38>
 3bc:	e51b0008 	ldr	r0, [fp, #-8]
 3c0:	e3a01000 	mov	r1, #0
 3c4:	e3a0201c 	mov	r2, #28
 3c8:	ebfffffe 	bl	0 <memset>
 3cc:	e51b3008 	ldr	r3, [fp, #-8]
 3d0:	e1a00003 	mov	r0, r3
 3d4:	e24bd004 	sub	sp, fp, #4
 3d8:	e8bd8800 	pop	{fp, pc}

000003dc <read_clock_cb>:
 3dc:	e92d4800 	push	{fp, lr}
 3e0:	e28db004 	add	fp, sp, #4
 3e4:	e24dd010 	sub	sp, sp, #16
 3e8:	e50b0010 	str	r0, [fp, #-16]
 3ec:	e50b1014 	str	r1, [fp, #-20]
 3f0:	e51b3010 	ldr	r3, [fp, #-16]
 3f4:	e5933020 	ldr	r3, [r3, #32]
 3f8:	e50b3008 	str	r3, [fp, #-8]
 3fc:	e51b3010 	ldr	r3, [fp, #-16]
 400:	e593301c 	ldr	r3, [r3, #28]
 404:	e5932000 	ldr	r2, [r3]
 408:	e51b3008 	ldr	r3, [fp, #-8]
 40c:	e2833004 	add	r3, r3, #4
 410:	e1a00002 	mov	r0, r2
 414:	e59f1060 	ldr	r1, [pc, #96]	; 47c <read_clock_cb+0xa0>
 418:	e59f2060 	ldr	r2, [pc, #96]	; 480 <read_clock_cb+0xa4>
 41c:	ebfffffe 	bl	0 <file_read_value>
 420:	e51b3010 	ldr	r3, [fp, #-16]
 424:	e593301c 	ldr	r3, [r3, #28]
 428:	e5932000 	ldr	r2, [r3]
 42c:	e51b3008 	ldr	r3, [fp, #-8]
 430:	e5933004 	ldr	r3, [r3, #4]
 434:	e59f0048 	ldr	r0, [pc, #72]	; 484 <read_clock_cb+0xa8>
 438:	e1a01002 	mov	r1, r2
 43c:	e59f2038 	ldr	r2, [pc, #56]	; 47c <read_clock_cb+0xa0>
 440:	ebfffffe 	bl	0 <printf>
 444:	e51b3008 	ldr	r3, [fp, #-8]
 448:	e5d3300c 	ldrb	r3, [r3, #12]
 44c:	e3530000 	cmp	r3, #0
 450:	0a000001 	beq	45c <read_clock_cb+0x80>
 454:	e59f302c 	ldr	r3, [pc, #44]	; 488 <read_clock_cb+0xac>
 458:	ea000000 	b	460 <read_clock_cb+0x84>
 45c:	e59f3028 	ldr	r3, [pc, #40]	; 48c <read_clock_cb+0xb0>
 460:	e59f0028 	ldr	r0, [pc, #40]	; 490 <read_clock_cb+0xb4>
 464:	e1a01003 	mov	r1, r3
 468:	ebfffffe 	bl	0 <printf>
 46c:	e3a03000 	mov	r3, #0
 470:	e1a00003 	mov	r0, r3
 474:	e24bd004 	sub	sp, fp, #4
 478:	e8bd8800 	pop	{fp, pc}
 47c:	000000e8 	andeq	r0, r0, r8, ror #1
 480:	000000f4 	strdeq	r0, [r0], -r4
 484:	000000f8 	strdeq	r0, [r0], -r8
 488:	0000011c 	andeq	r0, r0, ip, lsl r1
 48c:	00000124 	andeq	r0, r0, r4, lsr #2
 490:	0000012c 	andeq	r0, r0, ip, lsr #2

00000494 <fill_clock_cb>:
 494:	e92d4800 	push	{fp, lr}
 498:	e28db004 	add	fp, sp, #4
 49c:	e24dd010 	sub	sp, sp, #16
 4a0:	e50b0010 	str	r0, [fp, #-16]
 4a4:	e50b1014 	str	r1, [fp, #-20]
 4a8:	ebfffffe 	bl	394 <clock_alloc>
 4ac:	e50b0008 	str	r0, [fp, #-8]
 4b0:	e51b3008 	ldr	r3, [fp, #-8]
 4b4:	e3530000 	cmp	r3, #0
 4b8:	1a000001 	bne	4c4 <fill_clock_cb+0x30>
 4bc:	e3e03000 	mvn	r3, #0
 4c0:	ea00000f 	b	504 <fill_clock_cb+0x70>
 4c4:	e51b3010 	ldr	r3, [fp, #-16]
 4c8:	e51b2008 	ldr	r2, [fp, #-8]
 4cc:	e5832020 	str	r2, [r3, #32]
 4d0:	e51b3010 	ldr	r3, [fp, #-16]
 4d4:	e5933010 	ldr	r3, [r3, #16]
 4d8:	e3530000 	cmp	r3, #0
 4dc:	1a000004 	bne	4f4 <fill_clock_cb+0x60>
 4e0:	e51b3008 	ldr	r3, [fp, #-8]
 4e4:	e3a02001 	mov	r2, #1
 4e8:	e5c3200c 	strb	r2, [r3, #12]
 4ec:	e3a03000 	mov	r3, #0
 4f0:	ea000003 	b	504 <fill_clock_cb+0x70>
 4f4:	e51b0010 	ldr	r0, [fp, #-16]
 4f8:	e51b1014 	ldr	r1, [fp, #-20]
 4fc:	ebfffffe 	bl	3dc <read_clock_cb>
 500:	e1a03000 	mov	r3, r0
 504:	e1a00003 	mov	r0, r3
 508:	e24bd004 	sub	sp, fp, #4
 50c:	e8bd8800 	pop	{fp, pc}

00000510 <fill_clock_tree>:
 510:	e92d4800 	push	{fp, lr}
 514:	e28db004 	add	fp, sp, #4
 518:	e59f301c 	ldr	r3, [pc, #28]	; 53c <fill_clock_tree+0x2c>
 51c:	e5933000 	ldr	r3, [r3]
 520:	e1a00003 	mov	r0, r3
 524:	e59f1014 	ldr	r1, [pc, #20]	; 540 <fill_clock_tree+0x30>
 528:	e3a02000 	mov	r2, #0
 52c:	ebfffffe 	bl	0 <tree_for_each>
 530:	e1a03000 	mov	r3, r0
 534:	e1a00003 	mov	r0, r3
 538:	e8bd8800 	pop	{fp, pc}
	...

Disassembly of section .rodata:

00000000 <.rodata>:
   0:	25732a25 	ldrbcs	r2, [r3, #-2597]!	; 0xa25
   4:	00000a73 	andeq	r0, r0, r3, ror sl
   8:	0000002d 	andeq	r0, r0, sp, lsr #32
   c:	006b6c63 	rsbeq	r6, fp, r3, ror #24
  10:	31335b1b 	teqcc	r3, fp, lsl fp
  14:	72655b6d 	rsbvc	r5, r5, #111616	; 0x1b400
  18:	203a5d72 	eorscs	r5, sl, r2, ror sp
  1c:	6d305b1b 	fldmdbxvs	r0!, {d5-d17}	;@ Deprecated
  20:	74756f72 	ldrbtvc	r6, [r5], #-3954	; 0xf72
  24:	6e695f65 	cdpvs	15, 6, cr5, cr9, cr5, {3}
  28:	202c6f66 	eorcs	r6, ip, r6, ror #30
  2c:	6c6c616d 	stfvse	f6, [ip], #-436	; 0xfffffe4c
  30:	6620636f 	strtvs	r6, [r0], -pc, ror #6
  34:	646c6961 	strbtvs	r6, [ip], #-2401	; 0x961
  38:	00000000 	andeq	r0, r0, r0
  3c:	6d6f682f 	stclvs	8, cr6, [pc, #-188]!	; ffffff88 <fill_clock_tree+0xfffffa78>
  40:	68732f65 	ldmdavs	r3!, {r0, r2, r5, r6, r8, r9, sl, fp, sp}^
  44:	796c696d 	stmdbvc	ip!, {r0, r2, r3, r5, r6, r8, fp, sp, lr}^
  48:	676f622f 	strbvs	r6, [pc, -pc, lsr #4]!
  4c:	632f6e6f 	teqvs	pc, #1776	; 0x6f0
  50:	6b636f6c 	blvs	18dbe08 <fill_clock_tree+0x18db8f8>
  54:	65657254 	strbvs	r7, [r5, #-596]!	; 0x254
  58:	6b6c632f 	blvs	1b18d1c <fill_clock_tree+0x1b1880c>
  5c:	00000000 	andeq	r0, r0, r0
  60:	31335b1b 	teqcc	r3, fp, lsl fp
  64:	72655b6d 	rsbvc	r5, r5, #111616	; 0x1b400
  68:	203a5d72 	eorscs	r5, sl, r2, ror sp
  6c:	6d305b1b 	fldmdbxvs	r0!, {d5-d17}	;@ Deprecated
  70:	6e616373 	mcrvs	3, 3, r6, cr1, cr3, {3}
  74:	20732520 	rsbscs	r2, r3, r0, lsr #10
  78:	6c696166 	stfvse	f6, [r9], #-408	; 0xfffffe68
  7c:	00000a64 	andeq	r0, r0, r4, ror #20
  80:	34335b1b 	ldrtcc	r5, [r3], #-2843	; 0xb1b
  84:	6e695b6d 	vnmulvs.f64	d21, d9, d29
  88:	203a5d66 	eorscs	r5, sl, r6, ror #26
  8c:	6d305b1b 	fldmdbxvs	r0!, {d5-d17}	;@ Deprecated
  90:	20797274 	rsbscs	r7, r9, r4, ror r2
  94:	73206f74 	teqvc	r0, #464	; 0x1d0
  98:	206e6163 	rsbcs	r6, lr, r3, ror #2
  9c:	65726964 	ldrbvs	r6, [r2, #-2404]!	; 0x964
  a0:	726f7463 	rsbvc	r7, pc, #1660944384	; 0x63000000
  a4:	73252079 	teqvc	r5, #121	; 0x79
  a8:	0000000a 	andeq	r0, r0, sl
  ac:	31335b1b 	teqcc	r3, fp, lsl fp
  b0:	72655b6d 	rsbvc	r5, r5, #111616	; 0x1b400
  b4:	203a5d72 	eorscs	r5, sl, r2, ror sp
  b8:	6d305b1b 	fldmdbxvs	r0!, {d5-d17}	;@ Deprecated
  bc:	62616e75 	rsbvs	r6, r1, #1872	; 0x750
  c0:	7420656c 	strtvc	r6, [r0], #-1388	; 0x56c
  c4:	706f206f 	rsbvc	r2, pc, pc, rrx
  c8:	64206e65 	strtvs	r6, [r0], #-3685	; 0xe65
  cc:	63657269 	cmnvs	r5, #-1879048186	; 0x90000006
  d0:	79726f74 	ldmdbvc	r2!, {r2, r4, r5, r6, r8, r9, sl, fp, sp, lr}^
  d4:	0a732520 	beq	1cc955c <fill_clock_tree+0x1cc904c>
  d8:	00000000 	andeq	r0, r0, r0
  dc:	00007325 	andeq	r7, r0, r5, lsr #6
  e0:	252f7325 	strcs	r7, [pc, #-805]!	; fffffdc3 <fill_clock_tree+0xfffff8b3>
  e4:	00000073 	andeq	r0, r0, r3, ror r0
  e8:	5f6b6c63 	svcpl	0x006b6c63
  ec:	65746172 	ldrbvs	r6, [r4, #-370]!	; 0x172
  f0:	00000000 	andeq	r0, r0, r0
  f4:	00007525 	andeq	r7, r0, r5, lsr #10
  f8:	34335b1b 	ldrtcc	r5, [r3], #-2843	; 0xb1b
  fc:	6e695b6d 	vnmulvs.f64	d21, d9, d29
 100:	203a5d66 	eorscs	r5, sl, r6, ror #26
 104:	6d305b1b 	fldmdbxvs	r0!, {d5-d17}	;@ Deprecated
 108:	64616572 	strbtvs	r6, [r1], #-1394	; 0x572
 10c:	2f732520 	svccs	0x00732520
 110:	202c7325 	eorcs	r7, ip, r5, lsr #6
 114:	48207525 	stmdami	r0!, {r0, r2, r5, r8, sl, ip, sp, lr}
 118:	00000a7a 	andeq	r0, r0, sl, ror sl
 11c:	65757274 	ldrbvs	r7, [r5, #-628]!	; 0x274
 120:	00000000 	andeq	r0, r0, r0
 124:	736c6166 	cmnvc	ip, #-2147483623	; 0x80000019
 128:	00000065 	andeq	r0, r0, r5, rrx
 12c:	34335b1b 	ldrtcc	r5, [r3], #-2843	; 0xb1b
 130:	6e695b6d 	vnmulvs.f64	d21, d9, d29
 134:	203a5d66 	eorscs	r5, sl, r6, ror #26
 138:	6d305b1b 	fldmdbxvs	r0!, {d5-d17}	;@ Deprecated
 13c:	61707865 	cmnvs	r0, r5, ror #16
 140:	6465646e 	strbtvs	r6, [r5], #-1134	; 0x46e
 144:	0a732520 	beq	1cc95cc <fill_clock_tree+0x1cc90bc>
 148:	00000000 	andeq	r0, r0, r0

Disassembly of section .comment:

00000000 <.comment>:
   0:	43434700 	movtmi	r4, #14080	; 0x3700
   4:	6328203a 	teqvs	r8, #58	; 0x3a
   8:	73736f72 	cmnvc	r3, #456	; 0x1c8
   c:	6c6f6f74 	stclvs	15, cr6, [pc], #-464	; fffffe44 <fill_clock_tree+0xfffff934>
  10:	20474e2d 	subcs	r4, r7, sp, lsr #28
  14:	35312e31 	ldrcc	r2, [r1, #-3633]!	; 0xe31
  18:	2029322e 	eorcs	r3, r9, lr, lsr #4
  1c:	2e372e34 	mrccs	14, 1, r2, cr7, cr4, {1}
  20:	30322031 	eorscc	r2, r2, r1, lsr r0
  24:	34303231 	ldrtcc	r3, [r0], #-561	; 0x231
  28:	28203230 	stmdacs	r0!, {r4, r5, r9, ip, sp}
  2c:	72657270 	rsbvc	r7, r5, #7
  30:	61656c65 	cmnvs	r5, r5, ror #24
  34:	00296573 	eoreq	r6, r9, r3, ror r5

Disassembly of section .ARM.attributes:

00000000 <.ARM.attributes>:
   0:	00003f41 	andeq	r3, r0, r1, asr #30
   4:	61656100 	cmnvs	r5, r0, lsl #2
   8:	01006962 	tsteq	r0, r2, ror #18
   c:	00000035 	andeq	r0, r0, r5, lsr r0
  10:	4d524105 	ldfmie	f4, [r2, #-20]	; 0xffffffec
  14:	36373131 			; <UNDEFINED> instruction: 0x36373131
  18:	2d465a4a 	vstrcs	s11, [r6, #-296]	; 0xfffffed8
  1c:	07060053 	smlsdeq	r6, r3, r0, r0
  20:	01090108 	tsteq	r9, r8, lsl #2
  24:	0412020a 	ldreq	r0, [r2], #-522	; 0x20a
  28:	01150114 	tsteq	r5, r4, lsl r1
  2c:	01180317 	tsteq	r8, r7, lsl r3
  30:	021a0119 	andseq	r0, sl, #1073741830	; 0x40000006
  34:	011c031b 	tsteq	ip, fp, lsl r3
  38:	0122061e 	teqeq	r2, lr, lsl r6
  3c:	0144012c 	cmpeq	r4, ip, lsr #2
